1. Technical Field
The present invention relates to a layout of active pixel sensor arrays and, more particularly, to a layout of a complementary metal-oxide semiconductor (CMOS) active pixel sensor array having a shared structure in which a plurality of active pixel sensors share a reset transistor and readout transistors.
2. Description of the Related Art
An active pixel sensor is a device for transforming a photo image into an electrical signal. Active pixel sensors are widely used in digital cameras, camera-mounted mobile phones, visual systems, etc.
The active pixel sensor may be broadly classified into a charge-coupled device (CCD) active pixel sensor type and a complementary metal-oxide semiconductor (CMOS) active pixel sensor type. The CCD active pixel sensor type generally exhibits less noise and better image quality than the CMOS active pixel sensor type, but the production costs and power consumption are higher for the CCD type as compared to the CMOS type. The CMOS active pixel sensor type, which may be produced using conventional semiconductor manufacturing technology, may be provided at low costs, for example, due to ease of integration with peripheral systems for amplifying and processing signals.
Typical configurations of the CMOS active pixel sensor include 3-transistor and 4-transistor configurations. According to the 4-transistor configuration, one CMOS active pixel sensor includes one photo diode and four transistors. In the 4-transistor configuration, the integrated charge that is collected by the photo diode is transferred through the four transistors. In the 3-transistor configuration, one CMOS active pixel sensor includes one photo diode and three transistors, and the integrated charge that is collected by the photo diode is transferred through the three transistors.
FIG. 1 is a circuit diagram illustrating a conventional 4-transistor CMOS active pixel sensor. Referring to FIG. 1, the 4-transistor CMOS active pixel sensor 100 includes a photo diode PD, a transfer transistor M11, a reset transistor M12, a source follower transistor M13, and a select transistor M14.
When the reset transistor M12 is turned on according to a voltage rise of a gate RG, a voltage of a sensing node, i.e., a floating diffusion node FD is increased to a driving voltage VDD. At that point, the voltage of the floating diffusion node FD is sampled as a reference voltage by means of the source follower transistor M13 and the select transistor M14.
During an integration period, electron-hole pairs are generated in proportion to the light that is incident on the photo diode PD. After integration, the collected charge is transferred to the floating diffusion node FD according to a voltage rise of a gate TG of the transfer transistor M11. When the voltage of the floating diffusion node FD is decreased in proportion to the transferred charge, a source voltage of the source follower transistor M13 is changed.
Finally, when the select transistor M14 is turned on according to a rise of a gate SEL of the select transistor M14, the source voltage of the source follower transistor M13 is output as an output signal Vout. An accepted light is sensed by a voltage difference between the reference voltage and the output signal Vout, and this process is referred to as a correlated double sampling. Correlated double sampling yields a representation of the true charge associated with each pixel.
FIG. 2 is a circuit diagram illustrating a conventional 3-transistor CMOS active pixel sensor. Referring to FIG. 2, the 3-transistor CMOS active pixel sensor 200 includes a photo diode PD, a transfer transistor M21, a reset transistor M22 and a source follower transistor M23.
In the CMOS active pixel sensor 200 of FIG. 2, a dynamic driving voltage DVD is used instead of excluding the select transistor M14 from the CMOS active pixel sensor 100 of FIG. 1. The dynamic driving voltage DVD is increased to a high level when the floating diffusion node FD is reset and when a voltage of the floating diffusion node FD is sensed, but is generally maintained at a low level. Therefore, the select transistor M14 may be substituted using the dynamic driving voltage DVD.
When the dynamic driving voltage DVD reaches the high level and a gate RG voltage of the reset transistor M22 is increased to turn on the reset transistor M22, a voltage of the floating diffusion node FD is increased. At that point, the voltage of the floating diffusion node FD is sampled as a reference voltage by means of the source follower transistor M23 to be outputted to an internal circuit (not shown) for processing output signals of the active pixel sensors. After the reference voltage is output, the dynamic driving voltage is decreased to the low level.
Integration and charge transfer functions take place within the CMOS active pixel sensor as described above.
Recently, a shared structure, wherein a reset transistor, source follower transistor and select transistor may be shared, has been used for the purpose Of reducing a pixel size and enhancing a fill factor. The fill factor corresponds to a ratio of an area occupied by the photo diode with respect to an area occupied by peripheral circuits for resetting and outputting a sensed signal including a reset transistor, a source follower transistor and a select transistor. In general, the shared structure has been used for increasing the area of the photo diode by sharing transistors that perform the functions of amplifying and transferring signals.
FIG. 3 is a top plan view illustrating a conventional layout of a 4-transistor CMOS active pixel sensor array having a 4-pixel shared structure. The configuration of the 4-transistor CMOS active pixel sensor array of FIG. 3 is modified from the 4-transistor CMOS active pixel sensor of FIG. 1 so that a reset transistor, a source follower transistor and select transistor may be shared.
Referring to FIG. 3, the layout 300 of a 4-transistor CMOS active pixel sensor array includes a first photo diode region PD1, a second photo diode region PD2, a third photo diode region PD3 and a fourth photo diode region PD4. The layout 300 of a 4-transistor CMOS active pixel sensor array further includes four transfer transistors M31, M32, M33 and M34. The four photo diode regions and the four transfer transistors share a floating diffusion node FD, i.e., a drain region of the four transfer transistors forms a floating diffusion node FD.
A reset transistor M35, which resets a voltage of the floating diffusion node FD, is located between the third photo diode region PD3 and the fourth photo diode region PD4. A source follower transistor M36 and a select transistor M37 are located between the first photo diode region PD1 and the second photo diode region PD2. The source follower transistor M36 performs a sampling of the voltage of the floating diffusion node FD, and the select transistor M37 transfers a source voltage of the source follower transistor M36 to an internal circuit (not shown). The internal circuit (not shown) may be a circuit for processing output signals of the active pixel sensors.
In the layout of the shared structure, consideration may be given to maintaining an optical symmetry of the structure and enhancing the availability and productivity of a manufacturing process. In general, there are limitations to forming the layout of the active pixel sensor array having a shared structure. For example, in a configuration in which the floating diffusion node is shared, “steps” between the pixels along object edges may occur due to the layout itself or the manufacturing process.